In some integrated circuit fabrication processes, wafer polishing processes (e.g., scrubber cleaning and/or backside/bevel cleaning processes) may use etching techniques or a combination of chemical and mechanical processes (e.g., CMP) to polish and clean surfaces of a wafer (e.g., the backside and bevel of the wafer). Generally, wafer polishing processes may be used to achieve an even, flat topography on surfaces of the wafer. A flat wafer surface is desirable for improving subsequent process steps, such as for improving photo overlay accuracy. However, conventional wafer polishing processes may be limited by the etching techniques in its ability to achieve a truly flat wafer surface. Furthermore, conventional wafer polishing processes may cause damage, such as cracks or peeling, to surfaces of the wafer.